There have been so-called active matrix driving devices which drive, for instance, liquid crystal display panels and organic EL display panels and are constructed in such a manner that a thin-film transistor (TFT) made of amorphous silicon (amorphous Si; a-Si) or polycrystalline silicon (p-Si) is formed on a glass substrate. In connection with this, researches have been made on silicon devices with higher performance, aiming for integrating systems such as a peripheral driver, high-performance memory, microprocessor, image processor, and timing controller.
In recent years, peripheral drivers which are integrated using polycrystalline silicon having high mobility and operating at high speed have come into use. However, polycrystalline silicon has a localized state in the gap, which is caused due to reasons such as incomplete crystallinity and the defects around the crystal grain boundary, so that the mobility decreases and S-coefficient (subthreshold coefficient) increases. For this reason, the performance of a transistor made of polycrystalline silicon is insufficient to form a high-performance device required for integrating systems such as a high-performance peripheral driver, memory, microprocessor, image processor, and timing controller.
To form a high-performance device on an active matrix driving device, researches have been made on a technology to form a semiconductor device in such a way that a device made of single-crystal silicon thin film, such as a thin-film transistor, is formed in advance, and then this device is adhered on an insulating substrate (e.g. International Publication No. WO93/15589 and J. P. Salerno, Single Crystal silicon AMLCDs, Conference Record of the 1994 International Display Research Conference(IDRC) p.39-44(1994)).
For instance, the above-mentioned Japanese National Publication discloses such an example that a semiconductor device, which is manufactured by transferring a single-crystal silicon thin-film transistor which has been made in advance onto an insulating substrate onto a glass substrate using an adhesive, is utilized for a display panel of an active matrix liquid crystal display device.
Also, as an example of a method of manufacturing an SOI (Silicon On Insulator) wafer, Japanese Laid-Open Patent Application No. 7-235651/1995 (published on Sep. 5, 1995) discloses such a method that an epitaxial silicon layer is grown on porous Si, the epitaxial silicon layer is bonded with a handle wafer, and then separated from the porous silicon layer (Q. Y. Tong & U. Gesele, SEMICONDUCTOR WAFER BONDING: SCIENCE AND TECHNOLOGY, John Wiley & Sons, New York (1999)).
In the meantime, researches have also been made in the field of integrated circuits on an SOI technology to separate a thin single-crystal silicon layer at an oxidized film, in order to further causing a bulk silicon device to speed-up and consume lower amount of power. Concerning this, there is a technique for forming an SOI wafer, arranged such that a silicon or quartz handle wafer with an oxidized film thereon is bonded with single-crystal silicon, and then thinning these members so as to form an SOI (e.g. Japanese Laid-Open Patent Application No. 5-211128/1993 (published on Aug. 20, 1993). Furthermore, also for such devices, a technology for reducing the size of a transistor for the sake of improving performance and increasing the number of components per chip has been grown as in the case of bulk silicon devices (e.g. T. Matsumoto et al., International Electron Devices Meeting: Dec, pp.219-222 (2001)).
However, according to the conventional semiconductor devices and manufacturing methods thereof, there is a problem in heat resistance because a high-performance device formed from a single-crystal silicon thin film is adhered with a glass substrate using an adhesive. Due to this problem, there are limitations in the manufacturing process and device structure: For instance, it is impossible to form members such as a high-quality inorganic insulating film and TFT after carrying out adhering using an adhesive.
To solve this problem, a method of obtaining a silicon thin film by bonding a silicon wafer, to which hydrogen ions are implanted, with a crystallized glass substrate is disclosed by, for instance, Japanese Laid-Open Patent Application No. 8-262474/1996 (published on Oct. 11, 1996). However, this method adopts, as a substrate, a crystallized glass including atoms of alkali, thereby being expensive and inferior in workability. Furthermore, according to the method, the glass substrate has to be made from a 8-inch or 12-inch (Si) wafer, and hence it is not possible to adopt the method for a large-sized glass substrate (at least 300 mm×400 mm in size). On this account, from a cost/size point of view, it is very difficult to adopt the method disclosed by the above-mentioned publication to display devices.
On the other hand, active matrix substrates utilized for OLEDs (Organic Light Emitting Diodes) and liquid crystal display devices require most-advanced micro-fabrication technology to form parts (e.g. MPU) which have to be high-performance and highly-integrated. However, in the light of productivity, such active matrix substrates are still mainly made by forming a polycrystalline silicon on a large-sized glass substrate, so that the micro-fabrication necessary for obtaining high-performance and high-integration cannot sufficiently carried out. This is because of the problems such as the following: In consideration of the swell, irregularity in thickness, expansion and contraction (especially contraction), and the size of an exposure region, it is difficult to increase the reduction ratio of reduced projection exposure. Furthermore, the micro-fabrication is also limited by device characteristics, for instance, the fluctuation of the crystal grain boundary with respect to a transistor channel section is increased.
For the reasons above, it is extremely difficult to realize a device requiring high-performance and high-integration, such as an MPU, by adopting an arrangement of forming a polycrystalline silicon on a large-sized glass substrate.
As in the case of bulk silicon devices, SOI devices in the field of integrated circuits also require most-advanced micro-fabrication technology to form parts (e.g. MPU) which have to be high-performance and highly-integrated. Furthermore, to increase the number of components per chip, reduce power consumption (driving voltage), and improve working speed, it is necessary to miniaturize a transistor. To realize this, one has to take countermeasures against the decrease of a threshold voltage due to DIBL (Drain induced Barrier Lowering) and increase of S-value which is a short channel effect that is intensified as the miniaturization advances, and decrease of field effect due to quantum effect.
To restrain the short channel effect, it is considered that the reduction of the thickness of a silicon film is essential. For instance, according to A. Vandooren et al., “2002 IEEE international SOI Conference Proceedings”, a desirable thickness is about not more than 15-20 nm in the case of a MOS transistor having an SOI structure in which the gate length is not more than 0.1 micrometer.
To improve the characteristics of the transistor, meanwhile, it is necessary to reduce the thickness of a single-crystal silicon thin film and remove a damaged layer on the surface while keeping the thickness of the silicon thin film to be uniform. That is to say, a layer damaged due to reasons such as dangling bond and crystal defect, the layer being harmful in terms of electric properties, has to be removed without causing the fluctuation in the transistor characteristics, which is caused due to irregular thickness of the silicon thin film.
However, when only a part of the surface of an insulating film (e.g. SiO2 film) is covered with a single-crystal silicon thin film, it is impossible to use methods such as CMP. For this reason, when a single-crystal silicon thin-film device is formed only in a part of the surface of an insulating film, it has been extremely difficult to remove the damaged layer on the surface of the silicon thin film.